2018-12-29 13:04:17 +00:00
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#include "textflag.h"
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2019-10-10 08:29:40 +00:00
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// mul2 multiplicates FROM by 2, stores result in R1
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// and uses R1, R2 and R3 for internal computations.
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#define mul2(FROM, TO, R2, R3) \
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VPSLLQ $1, FROM, TO \
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VPALIGNR $8, TO, FROM, R2 \
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2021-12-28 12:24:46 +00:00
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VPSRLQ $63, R2, R2 \
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VMOVDQU ·x127x63(SB), R3 \
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VANDPD TO, R3, R3 \
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2019-10-10 08:29:40 +00:00
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VPUNPCKHQDQ R3, R3, R3 \
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2021-12-28 12:24:46 +00:00
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VXORPD R2, TO, TO \
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VXORPD R3, TO, TO
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2019-10-10 08:29:40 +00:00
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2019-10-15 11:37:59 +00:00
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#define mask(bit, src, tmp, to1, to2) \
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MOVQ src, tmp \
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SHRQ bit, tmp \
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ANDQ $1, tmp \
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NEGQ tmp \
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MOVQ tmp, to1 \
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VSHUFPS $0, to1, to1, to2
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// VPBROADCASTB to1, to2
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// Can't use VPBROADCASTB because it is AVX2 instruction
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//https://software.intel.com/en-us/forums/intel-isa-extensions/topic/301461
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#define mulBit(bit) \
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2021-12-28 12:24:46 +00:00
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VMOVDQU X0, X8 \
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VMOVDQU X2, X9 \
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2019-10-15 11:37:59 +00:00
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mul2(X0, X5, X6, X7) \
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VXORPD X1, X5, X0 \
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mul2(X2, X5, X6, X7) \
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VXORPD X3, X5, X2 \
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mask(bit, CX, DX, X6, X5) \
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VANDPD X0, X5, X1 \
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2021-12-28 12:24:46 +00:00
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VXORPD X8, X1, X1 \
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2019-10-15 11:37:59 +00:00
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VANDPD X2, X5, X3 \
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2021-12-28 12:24:46 +00:00
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VXORPD X9, X3, X3
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2019-10-15 11:37:59 +00:00
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2018-12-29 13:04:17 +00:00
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// func mulBitRight(c00, c01, c10, c11, e *[2]uint64)
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TEXT ·mulBitRight(SB),NOSPLIT,$0
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MOVQ c00+0(FP), AX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (AX), X0
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VMOVDQU X0, X8 // remember c00 value
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2018-12-29 13:04:17 +00:00
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MOVQ c01+8(FP), BX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (BX), X1
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2018-12-29 13:04:17 +00:00
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MOVQ c10+16(FP), CX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (CX), X2
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VMOVDQU X2, X9 // remember c10 value
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2018-12-29 13:04:17 +00:00
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MOVQ c11+24(FP), DX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (DX), X3
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2018-12-29 13:04:17 +00:00
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2019-10-15 11:37:59 +00:00
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mul2(X0, X5, X6, X7) // c00 *= 2
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VXORPD X5, X1, X0 // c00 += c01
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mul2(X2, X5, X6, X7) // c10 *= 2
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VXORPD X3, X5, X2 // c10 += c11
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MOVQ e+32(FP), CX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (CX), X5
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2019-10-15 11:37:59 +00:00
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VANDPD X0, X5, X1 // c01 = c00 + e
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2021-12-28 12:24:46 +00:00
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VXORPD X8, X1, X1 // c01 += X8 (old c00)
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2019-10-15 11:37:59 +00:00
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VANDPD X2, X5, X3 // c11 = c10 + e
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2021-12-28 12:24:46 +00:00
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VXORPD X9, X3, X3 // c11 += x9 (old c10)
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2018-12-29 13:04:17 +00:00
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2021-12-28 12:24:46 +00:00
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VMOVDQU X0, (AX)
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2019-10-15 11:37:59 +00:00
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MOVQ c10+16(FP), CX
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2021-12-28 12:24:46 +00:00
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VMOVDQU X2, (CX)
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VMOVDQU X1, (BX)
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VMOVDQU X3, (DX)
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2018-12-29 13:04:17 +00:00
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2019-10-15 11:37:59 +00:00
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RET
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2018-12-29 13:04:17 +00:00
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2019-10-15 11:37:59 +00:00
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TEXT ·mulByteRight(SB),NOSPLIT,$0
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MOVQ c00+0(FP), AX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (AX), X0
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2019-10-15 11:37:59 +00:00
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MOVQ c01+8(FP), BX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (BX), X1
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2019-10-15 11:37:59 +00:00
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MOVQ c10+16(FP), CX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (CX), X2
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2019-10-15 11:37:59 +00:00
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MOVQ c11+24(FP), DX
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2021-12-28 12:24:46 +00:00
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VMOVDQU (DX), X3
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2019-10-15 11:37:59 +00:00
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MOVB b+32(FP), CX
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2018-12-29 13:04:17 +00:00
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2019-10-15 11:37:59 +00:00
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mulBit($7)
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mulBit($6)
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mulBit($5)
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mulBit($4)
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mulBit($3)
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mulBit($2)
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mulBit($1)
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mulBit($0)
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2018-12-29 13:04:17 +00:00
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2021-12-28 12:24:46 +00:00
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VMOVDQU X0, (AX)
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2019-10-15 11:37:59 +00:00
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MOVQ c10+16(FP), CX
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2021-12-28 12:24:46 +00:00
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VMOVDQU X2, (CX)
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VMOVDQU X1, (BX)
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2019-10-15 11:37:59 +00:00
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MOVQ c11+24(FP), DX
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2021-12-28 12:24:46 +00:00
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VMOVDQU X3, (DX)
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2019-06-21 15:47:01 +00:00
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2019-10-15 11:37:59 +00:00
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RET
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